Device isolation typically is achieved by utilizing local oxidation of silicon ("LOCOS") or shallow trench isolation ("STI") techniques. In the STI device isolation technique, isolation commonly is provided by forming a recess or trench between two active areas, upon which the electronic devices are located, and filling the trench with an isolation material. Shallow trench isolation serves to provide higher packing density, improved isolation, and greater planarity, by avoiding the topographical irregularities encountered when using conventional thick film oxide isolation (LOCOS). In particular, the growth of thermal field oxide using a mask, such as nitride, creates an encroachment of the oxide into the active areas; this encroachment is referred to as the bird's beak effect.
Trench isolation technology includes a planarization process to remove oxide from the active areas and maintain oxide in the trenches. However, in some areas of the wafer face, there will be narrow trenches with narrow active areas between them, while in others there will be wide active areas and wider trenches. Various combinations of trench width and active area width occur, as well, at other places along the face of the wafer due to variations in circuit density. Because of these varying pattern densities, a sufficient degree of uniform planarization sometimes is not achieved. Improved planarity especially is important as device geometries shrink, reducing the photolithography depth of focus at subsequent patterning steps.
Several techniques specifically have been developed for planarization of wafer surfaces as part of trench isolation processing. For example, conformal oxide deposition with etchback has been used successfully to produce local smoothing and planarization, but etching into the trenches does occur when the technique is applied to wide trenches. Another technique for planarization employs spin-on photoresist or glasses, followed by etchback; again, the smoothing is dependent upon the trench geometries, and global planarization is not achieved when variable circuit density is encountered.
While prior techniques have been able to produce adequate planarization over local regions, none of the techniques have been able to accomplish global planarization over large areas of diverse trench patterns. Improved global planarity has been reported by using a two-layer photoresist approach, wherein the first layer is patterned to provide a uniform surface for coating by the second layer. The two layer stack then is etched back to the original level, leaving an essentially planar surface.
An improved resist etch-back technique using three resist layers also has been developed which offers enhanced planarity over the two-resist layers process. In the three-resist layer process, following deposition of a conformal oxide onto a wafer with patterned trenches, the first resist coat is patterned into the trenches to minimize the gap volume prior to the second resist coat, in a manner similar to the technique described above. The second coat then creates a relatively planar resist surface. However, due to photolithographic alignment considerations, there exists a set of trench widths that are too small to receive a resist block, and so the resist is too thin both in these small trenches and on adjacent small active areas. The second coat is therefore etched back in an oxygen chemistry, and a third resist coat is applied, which improves the planarity by increasing the amount of resist in the trenches without a resist block and on the adjacent small active areas. Following the third resist coat, the resist and oxide are then etched back to the silicon nitride with 1:1 selectivity.
Even with the three resist coats, the nonplanarity between the active area/trench regions with and without the resist block results in significant non-planarity across the die following the etch-back. Because of the thinner resist on active areas adjacent to trenches with no resist block, the oxide on these areas will clear first during the etch, and will continue to etch along the active area sidewall while waiting for larger active areas to clear. Another problem is that a final etch step with reduced resist etch rate is required to avoid punching through the trenches with no resist block, resulting in the appearance of oxide spikes adjacent to the active areas when the remaining resist above the trenches is subsequently stripped. The exposure of the active area sidewall and the oxide spikes can be avoided by leaving a small amount of oxide on the active areas, and performing a chemical mechanical polish until the oxide is completely removed from the nitride on all features. The polishing step smoothes the wafer surface and provides global planarization. The polishing step also makes the planarization process less sensitive to variations in localized resist non-planarity.
The combined resist etch-back with chemical mechanical polish process therefore offers a signifantly improved shallow-trench isolation process, but there are still several problems associated with the technique 1) the multiple resist coats and etches associated with resist etch-back result in accumulated tolerances that make the process difficult to control, even with the final chemical mechanical polish step; 2) the final nitride thickness range varies significantly between various active area/trench structures, due to both resist etch-back (e.g., active area structures adjacent to trenches with no filler have less oxide and so will polish to nitride more quickly) and chemical mechanical polish (e.g., small isolated active areas will polish more rapidly than large and/or dense active areas, even with the significantly reduced step height provided by resist etch-back); the result is that a significantly thicker nitride layer remains on large active areas than on small active areas, and so following the nitride strip the step height will vary depending on the feature size and pattern density, and a fairly large step will remain adjacent to large active areas; 3) the field oxide will be polished in wide trenches during chemical mechanical polish (a phenomenon referred to as dishing), reducing the final global planarity; 4) some pad deformation will occur across very large active areas, requiring an extended overpolish to ensure removal of oxide from the center of these features; this increases the nitride thickness range described in problem (2), and worsens planarity due to the slower polish rate of the nitride relative to the field oxide; 5) the extent of the effects described in problems (2), (3), and (4), will vary from on chip design to another, depending on the size of the largest active area, the proximity of large active areas to one another, the spacing between small isolated active areas, and the largest trench width. These effects can be reduced but not eliminated with undesirable layout rules imposed on circuit designs.
Special problems are encountered in dealing with high aspect ratio trenches, encountered, for example, in sub-half micron technology. When depositing conformal oxide to fill a high aspect ratio trench, a verticle seam inherently occurs along the center of the trench where the outer surface of oxide layers deposited along opposing verticle trench walls meet. After the deposition of the conformal trench oxide, the oxide fill in the trenches then, typically, is annealed to effect densification of the oxide. Densification of the deposited oxide is required to enhance resistance of the oxide to etching during subsequent processing. This annealing step is conducted in a nitrogen atmosphere, in order to prevent oxidation of the silicon substrate beneath the trench oxide. Following densification, the wafer surface is planarized by means of resist etch-back techniques with a filler mask followed by resist strip, and polishing down to the nitride by means of chemical-mechanical polishing ("CMP"). The chemical-mechanical polishing step is followed by several wet etch steps using hydrofluroic acid ("HF"). These wet etch steps are required for the formation of the gate dielectric on the active area and post-CMP cleanup. During the HF etch operation, the above-mentioned seam running along the center of the trench, tends to etch faster than the contiguous oxide, eventually resulting in the formation of a groove along the top surface of the seam. The seam along the outer edges of the trench, where the oxide filler abuts the sidewalls of the trench, also is a weak point subject to excessive etching and attendant grooving. These seams which are exposed and opened up during etching may act as traps for polysilicon residue, during later processing, leading to polysilicon shorts between adjacent polysilicon lines in the finished chip circuitry. Secondly, a high wet etch rate of the deposited formal conformal oxide leads to considerable amount of recess in the trench oxide; the exposed corner of the active area mesas and the trench sidewall become part of the gate dielectric and may lead to lower gate oxide integrity.